A dynamic random access memory (DRAM) device includes a memory cell array. The memory cell array includes a number of memory cells, which are arranged in rows and columns. One memory cell is positioned at the intersection of each row and column. Each row of memory cells has an associated row line, ROW, and each column of memory cells has an associated pair of complementary digit lines, DIGIT and DIGIT_.
At certain times (e.g., prior to a READ operation), it is desirable to equalize the voltages present on the complementary digit lines. Accordingly, the memory cell array includes an equalization circuit coupled between each pair of complementary digit lines, which operates to equalize the voltage on the associated pair of complementary digit lines.
In current DRAMs, each pair of complementary digit lines is equalized using an equalization voltage, referred to as VCCP. VCCP has a voltage level that is based on an externally-supplied power supply voltage, VCC. For example, VCCP may be approximately equal to VCC plus a set voltage margin. According to some standards, VCCP=VCC+1.2 Volts (V).
VCC is prone to fluctuations. Accordingly, VCCP also is prone to fluctuations. VCCP is boosted higher than VCC to provide more robust circuit operation in light of the VCC fluctuations. Due in part to the power constraints, current DRAMs include NMOS gates to produce VCCP. NMOS-based designs often result in relatively large layout sizes, and accordingly relatively larger device sizes.